Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA

Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, +6

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Convolutional Neural NetworkEngineeringMachine LearningHardware AlgorithmComputer Architecture +16

TIME

Ming Cheng, Lixue Xia, Zhenhua Zhu, +4

Electrical EngineeringEngineeringEnergy EfficiencyNeural NetworkComputer Engineering +6

A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks

Miao Hu, Yiran Chen, J. Joshua Yang, +2

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

EngineeringNeurochipSocial SciencesSynapse DesignMemory Device +15

A Deep Learning Approach for Blind Drift Calibration of Sensor Networks

Yuzhi Wang, Anqi Yang, Pengjun Wang, +2

IEEE Sensors Journal

Convolutional Neural NetworkEngineeringMachine LearningEmbedded SensingRecovery Rate +14

Harmonica: A Framework of Heterogeneous Computing Systems With Memristor-Based Neuromorphic Computing Accelerators

Xiaoxiao Liu, Mengjie Mao, Beiye Liu, +8

IEEE Transactions on Circuits and Systems I Regular Papers

EngineeringComputer ArchitectureIntegrated CircuitsInline Calibration SchemeHardware Systems +15

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis

Qiaoyi Liu, Song Yao, Jia Wang, +4

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Hardware TrojanEngineeringHardware Verification LanguageInformation SecurityVerification +18

Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method

Zhenhua Zhu, Jilan Lin, Ming Cheng, +4

Energy Efficient RRAM Spiking Neural Network for Real Time Classification

Yu Wang, Tianqi Tang, Lixue Xia, +5

EngineeringMachine LearningNeural NetworkNeurochipSocial Sciences +15

FASTrust: Feature analysis for third-party IP trust verification

Song Yao, Jie Zhang, Qiaoyi Liu, +4

Hardware TrojanEngineeringHardware Verification LanguageInformation SecurityTrust Management Architecture +22

Communication Lower Bound in Convolution Accelerators

Yinhe Han, Yu Wang

EngineeringHardware AccelerationEdge ComputingHigh-performance ArchitectureLower Bound +11