High-efficiency crystalline silicon (Si) solar cells require textured surfaces for efficient light trapping. However, passivation of a textured surface to reduce carrier recombination is difficult. Here, we relate the electrical properties of cells fabricated on a KOH-etched, random pyramidal-textured Si surface to the nanostructure of the passivated contact and the textured surface morphology. The effects of both microscopic pyramidal morphology and nanoscale surface roughness on passivated contacts consisting of polycrystalline Si (poly-Si) deposited on top of an ultrathin, 1.5-2.2 nm, SiO_x layer are investigated. Using atomic force microscopy, we show a pyramid face, which is predominantly a Si(111) plane to be significantly rougher than a polished Si(111) surface. This roughness results in a nonuniform SiO_x layer as determined by transmission electron microscopy of a poly-Si/SiO_x contact. Our device measurements also show an overall more resistive and hence a thicker SiO_x layer over the pyramidal surface as compared to a polished Si(111) surface, which we relate to increased surface roughness. Using electron-beam-induced current measurements of poly-Si/SiO_x contacts, we further show that the SiO_x layer near the pyramid valleys is preferentially more conducting and hence likely thinner than over pyramid tips, edges, and faces. Hence, both the microscopic pyramidal morphology and nanoscale roughness lead to a nonuniform SiO_x layer, thus leading to poor poly-Si/SiO_x contact passivation. Finally, we report >21% efficient and ≥80% fill-factor front/back poly-Si/SiO_x solar cells on both single-side and double-side textured wafers without the use of transparent conductive oxide layers, and show that the poorer contact passivation on a textured surface is limited to boron-doped poly-Si/SiO_x contacts.

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