In this paper, the fabrication and electrical performance optimization of a four-levels vertically stacked Si_0.7Ge_0.3 channel nanowires gate-all-around transistor are explored in detail. First, a high crystalline quality and uniform stacked Si_0.7Ge_0.3/Si film is achieved by optimizing the epitaxial growth process and a vertical profile of stacked Si_0.7Ge_0.3/Si fin is attained by further optimizing the etching process under the HBr/He/O₂ plasma. Moreover, a novel ACT@SG-201 solution without any dilution at the temperature of 40 °C is chosen as the optimal etching solution for the release process of Si_0.7Ge_0.3 channel. As a result, the selectivity of Si to Si_0.7Ge_0.3 can reach 32.84 with a signature of "rectangular" Si_0.7Ge_0.3 extremities after channel release. Based on these newly developed processes, a 4-levels vertically stacked Si_0.7Ge_0.3 nanowires gate-all-around device is prepared successfully. An excellent subthreshold slope of 77 mV/dec, drain induced barrier-lowering of 19 mV/V, I_on/I_off ratio of 9 × 10⁵ and maximum of transconductance of ~83.35 μS/μm are demonstrated. However, its driven current is only ~38.6 μA/μm under V_DS = V_GS = -0.8 V due to its large resistance of source and drain (9.2 × 10⁵ Ω). Therefore, a source and drain silicide process is implemented and its driven current can increase to 258.6 μA/μm (about 6.7 times) due to the decrease of resistance of source and drain to 6.4 × 10⁴ Ω. Meanwhile, it is found that a slight increase of leakage after the silicide process online results in a slight deterioration of the subthreshold slope and I_on/I_off ratio. Its leakage performance needs to be further improved through the co-optimization of source and drain implantation and silicide process in the future.

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