Pulkit Khandelwal

A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery

Mike Harwood, N. Warke, R. S. Simpson et al. · 2007 · 146 citations

Engineering, Computer Engineering, Electrical Engineering +13

3.4 A 40/50/100Gb/s PAM-4 Ethernet transceiver in 28nm CMOS

K. Gopalakrishnan, Alan Ren, A. Tan et al. · 2016 · 61 citations

Engineering, Computer Engineering, Electrical Engineering +17

Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2V<inf>pp</inf> voltage-mode driver

Andrew Joy, Hugh Mair, Hae-Chang Lee et al. · 2011 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +12

Link Performance Investigation of Industry First 100G PAM4 IC Chipset with Real-time DSP for Data Center Connectivity

Mau-Chung Frank Chang, Sudeep Bhoja, J. Riani et al. · Optical Fiber Communication Conference · 2016 · 21 citations

Engineering, Computer Engineering, Electrical Engineering +14

A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOS

M.Q. Le, J. Gorecki, J. Riani et al. · 2017 · 16 citations

Engineering, Computer Engineering, Electrical Engineering +13