21:I[432972,["/_next/static/chunks/bb923814e1f4d2e9.js","/_next/static/chunks/dd3ee9f5b7716ca6.js","/_next/static/chunks/4204a0ae82542ca8.js","/_next/static/chunks/1270dead247da766.js","/_next/static/chunks/6e1aa89a642f40be.js","/_next/static/chunks/2d7aa753e81324a8.js","/_next/static/chunks/8ffd0b71567920d8.js","/_next/static/chunks/67ea6dfd21f16c5f.js","/_next/static/chunks/24eb4379f68013fd.js","/_next/static/chunks/b8cd775ffdf935bd.js","/_next/static/chunks/983103cd9eb7b428.js","/_next/static/chunks/263f2cdcb9aa2341.js","/_next/static/chunks/294b9525248c8e5f.js"],"default"] 22:T553,We proposed a 4-bit double SONOS memory with two ONO layers, 4 storage nodes, for ultimate multi-bit operation and firstly demonstrate 4-bit operation using the physically separated 4 storage nodes. By using CHEI/HHI program/erase, each node was easily programmed and erased without any detrimental interference among the nodes. In the gate length of 120nm, the read/write margins of ~0.8V for front side (FS) and ~1.1V for back side (BS) at V _DS =1.2V was obtained. The V _TH shifts of ~1.5V for both program/erase (P/E) were observed with the P/E conditions, V _D /V _FG =3/5V, 3/-4V for FS and VD/VBG=3.2/7V, 3.2/-5V for BS, respectively, with the duration of 1 ms. The V _TH windows of ~0.9V for FS and ~1.1V for BS were achieved even after 10 ⁴ P/E cycles

#	Concept	H-Index	Publications	Citations
1	Engineering	1	1	13
2	Applied Physics	1	1	13
3	Computer Engineering	1	1	13
4	Electrical Engineering	1	1	13
5	Computer Architecture	1	1	13

	Year	Citations

About

Top Concepts