This paper presents a mode-reconfigurable 2nd-order noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) featured with the ability of optimizing the noise transfer function (NTF) synchronously. Three operation modes, the energy-saving (ES) mode, the normal (NM) mode, and the high-resolution (HR) mode, can be supported by reconfiguring the resolution of the internal SAR ADC (N

${}_{\mathrm {SAR}}$

) and the oversampling rate (OSR), while the NTF optimization is realized by modulating locations of zeros and poles in the context of a specific mode to enhance the NS effect. The prototype ADC is fabricated in a 180-nm CMOS and operates under a 1.8-V supply. Operating at 5MS/s sampling rate, the ADC’s OSR can be configured as 8 or 16 in different operation modes, so its bandwidth can be configured as 312.5kHz or 156.25kHz. With N_SAR and OSR reconfigured to be 8-bit and 8 for the ES mode, it achieves a signal-to-noise and distortion ratio (SNDR) of 80.3dB and consumes

$201\mu $

W. Attributing to the NTF optimization, 27% power saving can be reached in the ES mode with respect to that when the optimization were disabled for the same SNDR. In the HR mode, N_SAR and OSR are set to be 9-bit and 16, respectively. And a SNDR of 93.3dB is obtained at the expense of consuming

$280\mu $

W. It is evidenced that the SNDR can be boosted by 6.4dB owe to the NTF optimization, resulting in an optimal SNDR-based Schreier figure-of-merit (FoM

${}_{\mathrm {S}}$

) of 180.8dB for the ADC. The values for N_SAR and OSR are determined to be 9-bit and 8 for the NM mode, and the achievable SNDR is 88.2dB. The occupied core area is 0.537 mm².

#	Concept	H-Index	Publications	Citations
1	Engineering	1	1	30
2	Computer Engineering	1	1	30
3	Noise	1	1	30

	Year	Citations

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